DFT Architect (AI Accelerator SoC)

Location: London - JJ Mack; Bristol - The Crescent

Company

hirify.global is a startup founded in 2022 developing chips and systems for high-speed inference on frontier AI models.

What you will do

• Own and define DFT architecture for a large AI accelerator SoC, including scan, compression, MBIST, LBIST, and boundary scan.
• Set DFT strategy, methodology, flow, and signoff criteria, and integrate DFT tools and flows into the wider EDA environment.
• Define hierarchical DFT for multi-core designs and large memory systems, including scan architecture, compression, ATPG, and memory test and repair.
• Establish power-aware and at-speed test strategies while partnering with RTL and physical design on integration and timing closure.
• Work with test and product engineering on ATPG pattern bring-up and debug on ATE, production test, and yield ramp.
• Mentor and guide DFT engineers.

Requirements

• Typically 8+ years of DFT experience for complex ASIC/SoC designs.
• Ownership of DFT architecture for at least one large tapeout.
• Deep expertise in scan, compression, ATPG, and MBIST.
• Experience with Synopsys or Tessent tools.
• Strong understanding of clocking, resets, power domains, and physical constraints.
• Experience with silicon bring-up, debug, and yield ramp.
• Ability to own ambiguous, high-impact problems, balance architectural thinking with hands-on execution, and set direction while staying close to implementation details.

Culture & Benefits

• Full-time role based in London or Bristol.
• Competitive salary reflecting experience and the specialist nature of the role.
• Meaningful equity and ownership.
• Private medical, dental and vision coverage, contributory pension, 25 days of holiday plus bank holidays, and life and critical illness insurance.
• Diverse and inclusive office environment with a commitment to Equal Employment Opportunity.
• Some roles may require additional eligibility checks for UK, US, and other international export-control compliance.