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7 дней назад

Senior Photonic Layout Engineer (AI)

150 000 - 230 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Senior Photonic Layout Engineer (AI): Owning photonic layout and tape-out flows for an integrated optical-electronic computing platform with an accent on PIC implementation, Cadence workflow development, and photonic-electronic integration. Focus on routing, DRC/LVS verification, foundry PDK integration, and turning research silicon into a manufacturable commercial system.

Location: Berkeley, California, United States

Salary: $150,000–$230,000 per year

Company

Early-stage photonic computing company developing an integrated optical-electronic platform for AI workloads, spanning photonic compute, electronic ICs, packaging, memory, and system architecture.

What you will do

  • Own the photonic layout flow from design implementation and routing through verification, sign-off, and tape-out release.
  • Establish a Cadence Photonics workflow for GlobalFoundries’ 45 nm process that is compatible with the electronic IC design flow.
  • Implement photonic and electronic layouts and routing in Cadence, resolving interfaces between the two domains.
  • Own netlisting, DRC/LVS, foundry PDK integration, and manufacturing-readiness requirements.
  • Work across PIC, EIC, packaging, and lab validation while connecting layout decisions to integrated system performance.
  • Help establish a complete design workflow within a small team and move research silicon toward a commercial product.

Requirements

  • Direct PIC design experience with substantial personal ownership of layout implementation, routing, and verification.
  • Strong hands-on Cadence experience, including practical work connecting photonic and electronic design flows.
  • Experience taking commercial photonic designs toward tape-out, with personal accountability for implementation and sign-off.
  • Practical ownership of foundry PDKs, design rules, netlisting, and DRC/LVS.
  • Strong understanding of silicon-photonics device physics, supported by device or circuit design and simulation experience.
  • Ability to work across PIC, EIC, packaging, and lab validation while understanding how layout decisions affect the integrated system.
  • Comfort with hands-on execution, broad responsibility, and establishing a design flow within a small team.

Nice to have

  • PhD candidates are considered for the Senior position.

Culture & Benefits

  • Early-stage environment with major design and integration decisions still open.
  • Direct collaboration with a technically deep founding team.
  • Ownership of a foundational component of a photonic computing platform.
  • Medical, vision, and dental insurance.
  • 401(k).

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