Senior AI Systems Architect/Researcher

Location: On-site in Hillsboro, Oregon, United States; additional locations in Folsom and Santa Clara, California, United States.

Annual salary: $195,200–$275,580 USD.

Company

hirify.global's Central Engineering Group Networking Architecture organization develops networking silicon and platform architecture for hyperscale data centers, cloud infrastructure, and AI workloads.

What you will do

• Analyze AI training and serving workloads, identify communication and memory bottlenecks, and translate findings into IP, offload engines, platform features, and architecture requirements.
• Drive hardware-software co-design across compute, DPU/IPU, NIC, SoC fabric, storage, and AI serving runtimes including vLLM and SGLang.
• Define architectures for xPU-to-xPU, xPU-to-storage, and cross-node data movement using packet processing, RDMA-class transport, and programmable networking.
• Investigate KV-cache transfer, disaggregated prefill/decode, model and tensor parallelism, communication collectives, and memory-hierarchy bottlenecks.
• Shape multi-generation compute, memory, and interconnect roadmaps and define scaling strategies, migration paths, and architecture requirements.
• Align networking, SoC fabric, firmware, operating system, driver, and performance-modeling teams around technical direction.

Requirements

• Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related STEM field with 5+ years of relevant experience, or a PhD in one of these fields with 2+ years of relevant experience.
• Experience with modern AI training and/or inference systems, including model architecture internals, hardware algorithm code design, serving runtimes, and large-scale memory and data-movement bottlenecks.
• Hands-on experience with inference and training serving stacks such as vLLM and SGLang, including disaggregated prefill/decode, model parallelism, tensor parallelism, and their communication patterns.
• Experience in computer architecture and system-level design focused on networking, interconnect, or memory subsystems.
• Proficiency in C, C++, and/or Python.
• Architectural vision across AI systems, networking, memory, and software; systems thinking across compute, memory, network, and software.
• Ability to influence without authority, make decisions under ambiguity, collaborate cross-functionally, maintain ownership, and translate customer workload needs into architectural innovations.
• Continuous learning across AI systems, inference runtimes, interconnects, memory technologies, and cloud infrastructure.

Nice to have

• Experience with memory hierarchy and system bottleneck analysis, including caches, memory controllers, bandwidth/latency tradeoffs, and the memory wall.
• Experience with RDMA/RoCE, InfiniBand, or equivalent high-performance networking and data-movement technologies.
• Experience with IPU, DPU, SmartNIC, or accelerator-centric SoCs in cloud and hyperscale environments.
• Familiarity with PCIe, CXL, and memory semantics for high-performance I/O.
• Experience defining architecture through silicon, platform software, or product shipment, including translating workload analysis into architecture requirements and new IP.
• Track record of cross-team technical leadership and influencing architecture and roadmap at a senior level.

Culture & Benefits

• On-site work model with Shift 1 United States hours.
• Competitive annual compensation, stock bonuses, health benefits, retirement benefits, and vacation.
• Benefits package available to employees and their families.
• Commitment to responsible business practices and ethical hiring.