aipythonc++schedulinghardware software co designcode generationcompiler optimizationmemory planning
Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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Зарплата и рынок
Средняя
$200к-300к/год
$190к$230кмедиана$300к
По похожим ролям (48) ~ $230к/год
На СНГ рынке: $4.2к/мес ($3.1к - $5.1к)
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Чётко очерченная специализированная роль предлагает хорошую зарплату, акции и работу над новой AI-платформой; главный компромисс - продукт и его аппаратная база ещё находятся на этапе разработки.
Compiler Engineer (AI): Building custom compiler backends that map large-model inference onto pre-silicon in-memory AI hardware with an accent on code generation, scheduling, memory planning, fusion, and dispatch. Focus on co-designing compiler and hardware abstractions, validating optimizations with simulators and FPGA prototypes, and improving measured utilization and inference latency.
Location: Hybrid in Mountain View, United States
Salary: $200K–$300K plus equity
Company
hirify.global is an applied AI company building foundational hardware and software for the semiconductor industry, AI infrastructure, and systems computing.
What you will do
Build compiler passes that transform lowered programs into code executed by custom AI hardware.
Own scheduling, memory planning, fusion, and dispatch for large-model inference, optimizing utilization and end-to-end latency.
Design compiler approaches from first principles for hardware that does not follow conventional CPU or GPU architectures.
Co-design compiler and hardware abstractions, providing constraints and feedback to hardware architects while the chip design evolves.
Validate optimizations using simulators, FPGA prototypes, and silicon, and maintain a trusted performance regression suite.
Coordinate with frontend compiler engineers to determine which operations are compiler-generated and which use hand-tuned kernels.
Requirements
Deep experience with compiler optimization or code generation for accelerators or other non-CPU targets, including scheduling, tiling, fusion, or resource allocation.
Comfort working close to hardware and reasoning about memory bandwidth, utilization, and asymptotic complexity.
Willingness to design compilation approaches from first principles when existing approaches do not fit the hardware.
Track record of shipping optimizations that improved a measured performance metric.
Experience building software for evolving hardware, from simulation through bring-up.
Fluency in Python and familiarity with C, C++, or Rust.
Nice to have
Experience with PyTorch's compilation stack, including TorchDynamo, FX, Inductor, or torch.export, or with ML compilers such as IREE, TVM, or XLA.
Experience compiling for in-memory, spatial, or other non-von-Neumann compute targets.
Background in hardware design tools such as logic synthesis or place-and-route.
Experience building or using cycle-level or performance simulators to guide optimization.
Open-source contributions to compiler or kernel infrastructure such as PyTorch, Triton, TVM, MLIR, or LLVM.
Publications or presentations on compiler or performance work at venues such as MLSys, ASPLOS, or CGO.
Culture & Benefits
Hybrid work based in Mountain View.
Competitive and equitable compensation with base salary, performance-based incentives, benefits, and equity.
Collaboration across offices in New York City, Silicon Valley, London, Copenhagen, and Seoul.
Inclusive workplace with equal employment opportunities and reasonable disability accommodations.
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