Design Verification Intern (SystemVerilog/UVM)

Location: Petah-Tikva, Israel; onsite

Company

hirify.global develops semiconductor solutions for enterprise, cloud, AI, and carrier data infrastructure.

What you will do

• Implement design and verification features for next-generation network switches.
• Develop complex object-oriented random verification environments with SystemVerilog and UVM.
• Write verification test plans and create tests using random techniques and coverage analysis.
• Debug simulation failures, identify root causes, and close code and functional coverage.
• Use scripting languages to automate repetitive tasks and improve development efficiency.
• Investigate and implement new protocols and features to tapeout-quality standards.

Requirements

• Pursuing a BS or MS degree in computer science, electrical engineering, or a related technical field.
• At least two years remaining before graduation.
• Good understanding of object-oriented programming and digital logic.
• Strong problem-solving, collaboration, and communication skills.
• Applicants must be eligible to access export-controlled technology and software under applicable U.S. export control laws; an export license review may be required.

Nice to have

• Experience or interest in SystemVerilog, UVM, Python, C++, and AI tools.

Culture & Benefits

• Competitive compensation and comprehensive benefits.
• Collaborative, transparent, and inclusive work environment.
• Resources and support for professional growth and development.
• Interview candidates may not use AI tools, transcription apps, automated note-taking bots, or real-time answer generators during interviews.