Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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Зарплата и рынок
Очень мало
106к-158к CAD/год
150к CAD190к CADмедиана240к CAD
По похожим ролям (49) ~ 190к CAD/год
52
Средняя вакансия
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Чёткие технические задачи, компания из сферы электроэнергетики и хорошие льготы - плюсы вакансии, но зарплата заметно ниже бенчмарка для похожих ролей и существенно снижает привлекательность предложения.
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Ниже рынкаАктуальный стекПонятные задачиХорошие льготыЭнергетическая инфраструктура
Оценка от Hirify AI
Мэтч & Сопровод
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Описание вакансии
Текст:
Hirify AI/Оригинал
TL;DR
RTL Engineer (VHDL/FPGA): Developing and supporting digital communication products, including SONET/VSN multiplexers, Ethernet circuit emulation gateways, synchronized network clocks, and Ethernet switches, with an accent on VHDL RTL design, FPGA development, and functional verification. Focus on designing test harnesses, analyzing digital logic timing, defining system specifications, and leading complex RTL projects for critical electric-power infrastructure.
Location: Burnaby, British Columbia, Canada; onsite position.
Salary: CAD 105,600–158,400 annually.
Company
hirify.global designs, manufactures, and supports products and systems that protect, monitor, control, and automate electric power systems.
What you will do
Lead complex VHDL RTL digital logic projects for FPGA-based communication products.
Develop and support SONET/VSN multiplexers with TDM interfaces, Ethernet circuit emulation gateways, synchronized network clocks, Ethernet switches, and related products.
Create and maintain RTL design documentation, design specifications, system specifications, project plans, and labor estimates.
Write test plans and develop test harnesses and stimulus for RTL functional verification.
Participate in or moderate peer reviews and collaborate with product managers and cross-discipline teams on new products and enhancements.
Requirements
Bachelor’s degree in Electrical Engineering, a related discipline, or an equivalent combination of education and experience.
5+ years of combined experience in RTL digital design with FPGAs using VHDL or Verilog.
Experience with Xilinx, Intel FPGA (Altera), Microchip (Microsemi/Actel), and Lattice Semiconductor tools.
Experience designing firmware with FPGA SoCs or microprocessors using C/C++.
Experience with simulation, synthesis, timing analysis of digital logic, and functional verification of RTL digital logic.
Knowledge of networking protocols, Ethernet (IEEE 802.3), MPLS, SONET, and precise timing technologies such as PTP (IEEE 1588), IRIG-B, and GPS.
Ability to work cooperatively in a team environment, rapidly learn new skills, assume new responsibilities, and mentor others.
Strong writing, technical documentation, and speaking skills.
Satisfactory background check results and negative drug test results.
Nice to have
Supervisory experience or training.
Experience with JIRA development processes, including DCP, closeout, standups, and sprints, as well as GitHub and Confluence.
Culture & Benefits
Work on practical, high-quality solutions that improve the safety, reliability, and economics of electric power systems.
Annual eligible-employee RRSP contribution, with support for personal contributions.
Health insurance covering medical, prescription, dental, vision, life, and disability insurance.
Statutory and personal holidays, annual vacation starting at 15 days, 9 paid sick days, parental leave covering up to 90% of regular earnings, and family medical and compassionate leave.
Apprenticeships, tuition assistance, engineering development programs, wellness support, and adoption assistance.
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