Senior Digital Designer (Front-End & Back-End, Cryo-CMOS)

Location: London, UK; full-time, permanent employee

Salary: Competitive salary and share options scheme

Company

hirify.global is a London-based quantum computing scale-up developing scalable quantum processors based on industrial-grade silicon chips.

What you will do

• Define microarchitectures and develop synthesizable RTL for ultra-low-power cryogenic digital control circuits.
• Perform Verilog-AMS co-simulation and integrate digital logic with analog and RF interfaces for qubit control and readout.
• Execute physical implementation, including floorplanning, power-grid synthesis, clock-tree synthesis, low-power synthesis, and multi-corner, multi-mode static timing analysis.
• Complete DRC, LVS, ERC, GDSII/OASIS generation, and full tape-out signoff.
• Design high-speed serial interconnects and complex finite-state-machine control logic for sub-Kelvin quantum computing systems.

Requirements

• Master’s degree or Ph.D. in electrical engineering, microelectronics, computer engineering, or a related technical field.
• At least 5 years of hands-on digital and mixed-signal IC design experience, including at least two tape-outs on advanced semiconductor nodes.
• Proficiency in Verilog, SystemVerilog, Verilog-AMS, or SystemVerilog-Real-Math for RTL, co-simulation, and testbench development.
• Experience with industry-standard EDA tools such as Cadence Virtuoso, Innovus, and Xcelium, and Synopsys Design Compiler.
• Experience with RTL-to-GDSII/OASIS implementation, physical signoff, clock-tree synthesis, power-grid synthesis, and MCMM STA.
• Strong knowledge of serial protocols, FSM design, and low-power techniques such as clock gating, power gating, and dynamic voltage scaling.

Nice to have

• Experience designing, modelling, or characterising CMOS circuits at sub-4.2 K temperatures.
• Experience integrating digital logic with ADCs, DACs, LNAs, AWGs, or other analog/RF interfaces.
• Knowledge of quantum control interfaces, pulse generation, error correction, or cryogenic spin-qubit electronics.
• Experience with UPF/CPF, formal LEC, power signoff, advanced process nodes, TCL or Python automation, DFT, or silicon bring-up.

Culture & Benefits

• Collaborative, interdisciplinary research and development environment.
• Competitive salary and share options scheme.
• Contributory pension and private medical insurance.
• Flexible working, life assurance, cycle-to-work scheme, and choice of laptop or equipment.
• Central London workplace within a team spanning London, Oxford, San Sebastián, and Sydney.