Lead Design Engineer - Verification (ASIC Verification)

Location: Nanjing, China; onsite

Company

hirify.global develops electronic design automation and semiconductor design technologies.

What you will do

• Contribute as a senior technical engineer on the IP verification team for high-performance Consumer PHYs, including eUSB2v2, USB4-PHY, PCIe, eDP/DP, and SATA.
• Develop and maintain UVM-based verification environments, including testbench architecture, agents, sequences, scoreboards, UVM register models, and checkers from block level through subsystem level.
• Create verification plans, functional coverage models, SVA assertions, corner-case and error-injection strategies, and drive coverage closure and signoff metrics.
• Run regressions with Xcelium and vManager, debug RTL and testbench failures using Verisium and SimVision, and track issues to root cause and closure.
• Apply low-power verification, CDC/RDC checks, X-propagation, gate-level simulation, formal techniques, and commercial VIP integration for serial protocols.
• Collaborate with firmware, design, project management, and global engineering groups on PHY bring-up, customer releases, lab support, and pre- and post-silicon debug.

Requirements

• BS or MS degree in Electrical Engineering, Computer Engineering, or a related field.
• At least 3 years of industry experience in digital or ASIC verification.
• Hands-on experience with SystemVerilog and UVM, including constrained-random verification, functional coverage, and assertion-based verification.
• Knowledge of at least one serial standard such as USB, DisplayPort, PCIe, or Ethernet, including link training, power management, and protocol layering.
• Experience with verification planning and coverage-driven signoff.
• Strong cross-functional communication skills in both English and Mandarin are required.

Nice to have

• Verification experience with high-speed serial interface IPs, including PHY, PCS, or controller designs.
• Experience with Xcelium, vManager, Verisium, JasperGold, or Palladium.
• Experience with UPF/CPF, gate-level simulation, mixed-signal co-simulation, and controller-plus-PHY subsystem verification.
• Scripting and automation skills with Python, Perl, Tcl, Makefile, or regression infrastructure; interest in AI-assisted verification.

Culture & Benefits

• Collaborate with engineering groups in Nanjing and multiple worldwide locations.
• Contribute to verification infrastructure, methodology, and quality assurance for customer releases.
• Support lab bring-up and pre- and post-silicon debugging for global customers.