Design Verification Intern (SystemVerilog/UVM)

Location: Singapore

Company

hirify.global develops ultra-low-power semiconductor solutions for wearables, medical devices, IoT products, and AI-powered edge applications.

What you will do

• Verify digital designs including multi-CPU systems-on-chip, digital signal processors, security hardware, and IoT logic.
• Develop test plans at block, subsystem, and chip levels and execute full-chip SoC verification.
• Build scalable, reusable SystemVerilog and UVM test benches, test cases, stimulus generators, and checkers.
• Automate randomized testing and scoreboarding while tracking functional and code coverage.
• Debug design and verification issues, perform root-cause analysis, and collaborate with design teams on fixes.
• Maintain verification quality in line with industry standards and project requirements.

Requirements

• Currently pursuing a B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
• Coursework in relevant digital design and verification areas.
• Familiarity with Verilog and SystemVerilog.
• Proficiency in Python, Perl, Tcl, or C/C++ and comfort working in a Linux/UNIX environment.
• Familiarity with AMBA AXI, AHB, and APB protocols.
• Strong analytical, debugging, problem-solving, communication, and collaboration skills.

Nice to have

• Experience or interest in edge-based AI inference.

Culture & Benefits

• Work with cross-functional teams spanning design, research, development, production, marketing, sales, and operations.
• Collaborate in an environment focused on innovation, continuous learning, and complex technical work.
• Contribute to energy-efficient semiconductor technology used in wearables, medical devices, IoT products, and edge AI applications.
• Work within the hirify.global values of Innovate, Collaborate, Focus, Learn, and Achieve.