Silicon Design - Flows and Methodology Intern (Python/SystemVerilog)

Location: Guadalajara, Mexico; hybrid work model with time split between the assigned hirify.global site and off-site work. Shift 1 (Mexico).

Company

hirify.global develops semiconductor products and silicon IP, including memory-related hirify.globallectual property and design technologies.

What you will do

• Assist with developing and documenting silicon design tools, flows, and methodologies.
• Analyze design efficiency and identify quality gaps to support improvements.
• Support automation and scalability across multiple silicon design projects.
• Collaborate with cross-functional teams on internal tool development and enablement.
• Contribute to hands-on projects involving memory-related IP and silicon design initiatives.

Requirements

• Currently pursuing a bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, Embedded Systems Engineering, or a related technical field, with at least one year remaining as an active student.
• At least 6 months of hands-on experience with Python and Unix.
• Foundational knowledge of integrated circuit design flow and microarchitecture fundamentals.
• Familiarity with RTL design, SystemVerilog, and tools, flows, and methodology development.
• Advanced English proficiency required.
• Must have unrestricted, permanent right to work in Mexico; visa or immigration sponsorship is not available.

Culture & Benefits

• Hybrid work model combining on-site and off-site work.
• Collaborative environment with cross-functional teams.
• Hands-on exposure to real-world silicon design challenges.
• Focus on continuous learning, disciplined execution, automation, and process improvement.