12 дней назад
Pre-Silicon Verification Engineer (AI)
53 200 - 98 800€
Вакансия из Hirify Global, списка международных tech-компанийДля мэтча и отклика нужен Plus
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Pre-Silicon Verification Engineer (AI) (ASIC/SystemVerilog): Developing verification plans, test benches, and environments for complex NIC, IPU, and AI hardware IPs and subsystems with an accent on pre-silicon validation, simulation, formal verification, and AI-assisted verification workflows. Focus on debugging failing tests, analyzing coverage and design behavior, and collaborating across architecture, design, DFT, emulation, and bring-up teams.
Location: Leixlip, Ireland. Hybrid work model with time split between the assigned site and off-site work.
Annual salary: €53,200–€98,800.
Company
's Central Engineering Group designs and verifies IPs and architectures for NIC, IPU, ASIC, networking, AI, cloud, and other specialized workloads.
What you will do
- Develop and execute IP verification plans covering microarchitecture specifications.
- Design test benches and verification environments for complex IPs and subsystems.
- Use simulation, formal property verification, and AI-assisted tools to validate functionality and analyze power, timing, and coverage.
- Debug failing pre-silicon tests, identify root causes, and implement corrective measures.
- Collaborate with architects, designers, DFT, emulation, and bring-up teams from block to system level.
- Maintain verification infrastructure, document test plans, and drive methodology improvements.
Requirements
- Bachelor's degree in electrical engineering, computer engineering, computer science, or a related field.
- 5+ years of functional design verification experience with ASIC, SoC, or FPGA designs.
- Expertise in SystemVerilog, OVM/UVM, and debugging tools.
- Experience creating IP test environments or using formal verification methods.
- Strong knowledge of digital design fundamentals and microarchitecture principles.
- Experience with coverage analysis, SystemVerilog Assertions, and verification methodologies.
Nice to have
- Master's or PhD in a relevant engineering or computer science field.
- Experience with Ethernet, IPSec, DTLS, MACSec, APB, and AXI protocols.
- Experience with SystemC, Python, Perl, Shell scripting, and AI integration in verification flows.
- Experience collaborating across teams on architectural improvements.
Culture & Benefits
- Work within a highly skilled, agile design and verification team.
- Use modern AI assistants and automation across planning, stimulus and checker development, coverage analysis, and debugging.
- Hybrid work model combining on-site and off-site work.
- Annual compensation package with additional pay components and benefits potentially available.
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