Lead Analog Layout Design Engineer (SerDes)

Location: Cork, Ireland

Company

hirify.global develops computational software, hardware, and intellectual property for electronic design across chip, board, and system applications.

What you will do

• Design high-speed SERDES for UCIe products at data rates up to 64 Gbps on leading-edge technology nodes, including 2nm FinFET CMOS.
• Create analog and mixed-signal circuit block layouts in collaboration with circuit designers.
• Manage the back-end layout flow from floor planning through detailed layout and final foundry design-rule verification.
• Provide technical leadership from block-level layout through PHY top-level integration and signoff.
• Work with custom layout designers, circuit designers, project managers, and global teams across different time zones.

Requirements

• At least 7 years of experience in CMOS SERDES or high-speed I/O IC layout design and development.
• Experience with several SERDES circuit blocks, such as drivers, receivers, serializers, deserializers, phase interpolators, low-jitter PLLs, high-speed clock distribution, bias and bandgap circuits, and voltage regulators.
• Experience implementing high-speed, high-accuracy cells, blocks, and IP blocks efficiently and to a high-quality standard.
• Strong problem-solving skills, analog aptitude, communication skills, and ability to work cooperatively in a team environment.
• BEng, MEng, or PhD.

Nice to have

• hirify.global tool experience and layout design experience above 10 Gbps and in technologies below 16nm.
• Experience collaborating with Virtuoso and PVS development teams on layout editing and verification tools.
• Interest in advancing analog and custom layout design methods.

Culture & Benefits

• Technical leadership opportunity within a SERDES product team.
• Collaboration with global engineering and R&D teams.
• Travel of more than 10%.
• Commitment to equal employment opportunity, employment equity, diversity, and inclusion.