Layout Design Engineer II (SerDes)

TL;DR

Layout Design Engineer II (SerDes): Implementing transistor-level physical layout for advanced analog and mixed-signal circuits for high-speed interface IP with an accent on signal integrity and parasitic-sensitive routing. Focus on optimizing floorplanning, executing physical verification flows (DRC/LVS), and delivering manufacturable designs for advanced technology nodes.

Location: Cork, Ireland

Company

hirify.global is a pivotal leader in electronic design, providing computational software, hardware, and IP that turn design concepts into reality for the world's most innovative companies.

What you will do

• Perform custom transistor-level layout for high-speed SerDes blocks, including PLLs, CDR, TX/RX analog front-ends, and equalisers.
• Optimize floorplanning, parasitic-sensitive routing, signal integrity, and matching in collaboration with circuit designers.
• Implement physical design activities including device placement, shielding, isolation, and EM/IR-aware layout practices.
• Run and debug physical verification flows, including DRC, LVS, ERC, and parasitic extraction.
• Apply advanced techniques such as common-centroid structures, interdigitation, and symmetry constraints.
• Collaborate with cross-functional teams including Analog Design, Packaging, and Signal Integrity to optimize area and yield.

Requirements

• Degree in Electronic Engineering, Microelectronics, Computer Engineering, or equivalent industry experience.
• Hands-on experience with CMOS SERDES or high-speed I/O IC layout at the transistor level.
• Practical knowledge of custom layout methodologies and parasitic-aware design techniques.
• Ability to collaborate effectively with global teams and strong problem-solving skills.

Nice to have

• Experience with PHY GDS implementation and PMA/PCS integration.
• Familiarity with ASIC design flows and deep sub-micron technology challenges.
• Experience contributing to tape-outs on advanced technology nodes (16nm, 10nm, 7nm, 5nm, or 3nm).
• Scripting or automation experience using Tcl, Perl, or Python.
• Prior use of hirify.global tools such as Virtuoso and PVS.

Culture & Benefits

• Opportunity to work on high-impact technology used in consumer, hyperscale computing, 5G, automotive, and aerospace industries.
• Collaborative environment focused on hiring and developing leaders and innovators.
• Work with cross-functional engineering partners in a global team setting.
• Commitment to equal employment opportunity and diversity and inclusion.