Manager ASIC Digital Design (RISC-V)

Location: Hsinchu, Taiwan

Company

hirify.global is a full-service semiconductor foundry providing design, development, and fabrication services with a global manufacturing footprint.

What you will do

• Lead ASIC design and verification teams for processor and interconnect subsystems.
• Define and drive UVM-based verification strategies and coverage closure.
• Deliver complex CPU and IP verification programs with high quality.
• Collaborate with architecture, RTL, modeling, and software teams across a global engineering organization.
• Drive cross-functional execution, influence technical decisions, and establish engineering best practices.
• Mentor and develop team members.

Requirements

• Bachelor’s or master’s degree in electrical engineering, computer engineering, or a related field.
• 10+ years of ASIC design and verification experience.
• 3+ years of team leadership experience.
• Strong knowledge of RISC-V, processor architecture, or interconnects.
• Expertise in UVM and SystemVerilog, with experience using simulation tools such as VCS or Questa.
• Strong leadership and communication skills.

Culture & Benefits

• Work in a multicultural and inclusive semiconductor engineering environment.
• Employment is subject to successful background checks, applicable medical screenings, and local laws.
• No recruitment fees are charged at any stage of the hiring process.