Senior/Staff Formal Verification Engineer

Location: Tel Aviv-Yafo, Tel Aviv District, Israel

Company

hirify.global develops semiconductor-based connectivity solutions and software for rack-scale AI infrastructure, integrating technologies such as CXL, Ethernet, NVLink, PCIe, and UALink.

What you will do

• Own and develop formal verification environments from initial setup through sign-off.
• Define formal verification strategies and apply formal methodologies to prove complex design correctness.
• Analyze RTL designs and build robust environments to identify corner-case bugs.
• Analyze verification failures and work directly with designers to resolve issues.
• Collaborate with Architecture, Design, and DV teams to identify verification needs and design requirements.
• Architect reusable formal functions and properties for multiple projects.

Requirements

• Bachelor's degree in Electrical Engineering or a related technical field.
• 4+ years of hands-on formal verification experience in semiconductor companies.
• Deep expertise in formal verification methodologies, tools, and flows.
• Strong understanding of RTL design and verification principles.
• Experience with industry-standard formal verification tools such as Jasper or VC Formal.
• Excellent communication, analytical, and problem-solving skills.

Nice to have

• Experience taking complex blocks or subsystems through the complete formal verification lifecycle.
• Experience with SystemVerilog UVM-based design verification.
• Knowledge of Ethernet, NVLink, UALink, or PCIe networking standards.
• Background in high-speed serial interface verification.

Culture & Benefits

• Opportunity to help establish a strategic R&D center in Israel.
• Meaningful product ownership in a newly expanding engineering site.
• Inclusive workplace encouraging applications from people with diverse backgrounds and experiences.