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3 дня назад

Principal Analog Design Engineer (SERDES)

Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
Ireland
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Principal Analog Design Engineer (SERDES) (High-Speed Analog/Mixed-Signal IC Design): Designing high-speed SERDES products at data rates up to and exceeding 112 Gbps on leading-edge CMOS technology nodes with an accent on analog circuit blocks, SERDES architectures, and customer-specification verification. Focus on designing jitter-sensitive circuits, signal equalization, PLLs, clock distribution, and other SERDES blocks while providing technical leadership to the PMA design team.

Location: Cork, Ireland

Company

hirify.global develops computational software, hardware, and intellectual property for electronic design across chip, board, and system applications.

What you will do

  • Design high-speed SERDES products supporting data rates up to and exceeding 112 Gbps on leading-edge technology nodes, including 5nm FinFET CMOS.
  • Design and develop analog and mixed-signal IC circuit blocks from initial concept and specification through final verification against customer requirements.
  • Collaborate with Physical Design Engineers on IC circuit blocks and PMA sections.
  • Provide technical leadership in circuit design and SERDES architectures.
  • Collaborate with global teams across the US and different time zones.

Requirements

  • At least 7 years of experience in CMOS SERDES or high-speed I/O IC design and development.
  • BEng, MEng, or PhD qualification.
  • Working knowledge of common SERDES standards and their electrical requirements.
  • Thorough understanding of jitter and signal equalization techniques.
  • Proficiency in multiple SERDES circuit blocks, including drivers, receivers, serializers, deserializers, phase interpolators, low-jitter PLLs, high-speed clock distribution, bias and bandgap circuits, and voltage regulators.
  • Strong problem-solving, analog design, communication, and teamwork skills.

Nice to have

  • Experience with hirify.global tools and design above 10 Gbps in technologies below 40nm.
  • Laboratory test experience during silicon evaluation.
  • Interest in publishing academic papers and presenting at conferences such as ISSCC and JSSC.

Culture & Benefits

  • Full-time position with more than 5% travel.
  • Equal employment opportunity and employment equity throughout the organization.
  • Commitment to a qualified, diverse, and inclusive workplace.

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