Sr Principal Design Engineer

Location: Shanghai, China

Company

hirify.global develops hardware and software solutions that enable advanced silicon architectures and system design.

What you will do

• Design, develop, and optimize C/C++ device drivers for high-speed hardware interfaces such as PCIe and CXL on Linux and Windows.
• Build and maintain GUI tools for device configuration, telemetry monitoring, validation, and real-time debugging.
• Analyze register maps, implement communication protocols, and integrate software with hardware systems.
• Implement device enumeration, configuration handling, interrupt processing, DMA functionality, and hardware-to-GUI control loops.
• Develop automation frameworks and test utilities for hardware bring-up, regression testing, and field debugging.
• Investigate complex hardware-software integration issues and collaborate with hardware, engineering, and customer enablement teams.

Requirements

• 10+ years of industry experience and a bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related field.
• Strong production-grade programming skills in C/C++.
• Hands-on experience developing device drivers for Linux and/or Windows.
• Foundational understanding of advanced protocols such as PCIe and Ethernet.
• Proven ability to debug complex system integration issues across hardware and software layers.

Nice to have

• Experience combining SystemVerilog, C/C++, and Python in multi-language systems.
• Experience with Qt, PyQt, or similar GUI frameworks and Python-based test automation.
• Linux kernel driver development, memory management, and user-mode hardware access with VFIO, UIO, or PCIe BAR mapping.
• Experience with protocol analyzers, logic analyzers, oscilloscopes, or AI/ML methods for hardware verification and tooling automation.

Culture & Benefits

• Full-time work within the Palladium and Protium solution team.
• Collaboration with hardware engineering and customer enablement teams.
• Opportunity to work on advanced interface and memory protocol technologies.