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Sr Principal Design Engineer

Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
China
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Sr Principal Design Engineer (RTL/Verilog): Designing, developing, and productizing protocol products such as PCIe and advanced Ethernet for Cadence’s flagship emulation and prototyping product line with an accent on RTL design, verification, and system integration. Focus on solving complex protocol, electrical, timing-closure, and RTL verification challenges across logic design, UVM-based verification, and board debug.

Location: Shanghai

Company

hirify.global develops flagship emulation and prototyping products for modern IC design and verification.

What you will do

  • Work in the hirify.global Flagship Emulation and Prototyping product line.
  • Design, develop, modify, and productize protocol products such as PCIe and advanced Ethernet.
  • Contribute as an individual contributor to protocol projects involving logic RTL design, UVM-based verification, board design and debug, and documentation.
  • Solve complex protocol and system-integration issues, including electrical and timing closure challenges.
  • Contribute to RTL design and verification methodologies.

Requirements

  • MSEE or equivalent degree with experience in logic design and debug.
  • Excellent written and verbal communication skills.
  • RTL design experience using Verilog.
  • Experience using RTL verification tools and flows.

Nice to have

  • Experience in FPGA design for Xilinx products.
  • UVM verification experience.
  • Experience with scripting languages such as Perl, TCL, and C-shell.

Culture & Benefits

  • Full-time position based in Shanghai.
  • Opportunity to work on technology intended to address complex problems in modern IC design and verification.
  • hirify.global emphasizes developing leaders and innovators who want to make an impact on technology.

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