Senior Design Verification Engineer (ASIC)

TL;DR

Senior Design Verification Engineer (ASIC/UVM): Driving functional verification of complex networking blocks for next-generation network switches with an accent on UVM and SystemVerilog. Focus on developing advanced verification components, testbenches, and implementing coverage-driven verification to ensure hardware reliability.

Location: Petah-Tikva, Israel

Company

hirify.global provides semiconductor solutions that serve as essential building blocks for data infrastructure across enterprise, cloud, AI, and carrier architectures.

What you will do

• Drive functional verification of complex networking blocks using UVM and SystemVerilog.
• Develop and maintain advanced verification components and testbenches.
• Collaborate with cross-functional teams, including architecture, design, firmware, and post-silicon.
• Contribute to the improvement of verification methodology and infrastructure in a dynamic environment.

Requirements

• B.Sc. or M.Sc. in Electrical or Computer Engineering.
• 7+ years of hands-on experience in ASIC/RTL verification.
• Strong proficiency in SystemVerilog and UVM methodology.
• Deep understanding of coverage-driven verification, object-oriented programming (OOP), and constrained random testing.
• Must be eligible to access export-controlled information as defined under U.S. export control laws (EAR).

Culture & Benefits

• Competitive compensation and comprehensive benefits package.
• Collaborative work environment emphasizing transparency and inclusivity.
• Dedicated resources for professional growth and career development.