Lead Design Engineer (ASIC)

TL;DR

Lead Design Engineer (ASIC): Physical design implementation for ASIC projects with an accent on floor planning, power grid design, and timing closure. Focus on leading next-generation physical design methodologies and optimizing low-power, high-speed designs at advanced technology nodes.

Location: Gyeonggi-do (Seoul), South Korea

Company

hirify.global is a global leader in electronic design automation (EDA) software and hardware solutions.

What you will do

• Perform full physical design implementation including floor planning, power grid design, place and route, and clock tree synthesis.
• Manage timing closure, power/signal integrity signoff, and physical verification (DRC/LVS/Antenna).
• Execute EM/IR signoff and DFM closure for high-complexity designs.
• Work on low power and high speed designs at the latest technology nodes.
• Lead the development of next-generation physical design methodologies and flows.
• Collaborate closely with the RTL design team to ensure successful tapeouts.

Requirements

• 6+ years of experience with ASIC design flow and hierarchical physical design strategies.
• Deep understanding of deep sub-micron technology issues.
• Solid knowledge of Low Power Design, DFT, static timing analysis, and closure.
• Expertise in EM/IR-Drop/crosstalk analysis, formal verification, and DFM.
• Ability to work independently and handle complex technical tasks hands-on.
• English: Good communication skills required

Culture & Benefits

• Opportunity to work on cutting-edge technology nodes and challenging designs.
• Collaborative environment focused on innovation and technical impact.
• Professional growth in a leading EDA company.