Physical Design Engineer

TL;DR

Physical Design Engineer: Implementing custom IP and SoC designs from RTL to GDS with an accent on synthesis, floor planning, and timing closure. Focus on optimizing designs for power, performance, and area while developing robust methodologies for semiconductor manufacturing.

Location: Must be based in Guadalajara, Mexico (Hybrid work model). Must have unrestricted, permanent right to work in Mexico; no visa sponsorship provided.

Company

hirify.global is a global leader in semiconductor technology, driving advancements in computing and data-driven engineering solutions.

What you will do

• Perform physical design implementation of custom IP and SoC designs from RTL to GDS.
• Execute comprehensive flows including synthesis, floor planning, place and route, and clock tree synthesis.
• Conduct signoff activities such as static timing analysis, power integrity, and formal equivalence verification.
• Analyze and resolve complex violations related to timing, reliability, and design structure.
• Optimize designs for power, performance, and area using industry-standard EDA tools.
• Develop and refine physical design methodologies and flow automation to improve efficiency.

Requirements

• Bachelor's degree with 3+ years of experience, Master's with 2+ years, or PhD in Electrical/Computer Engineering.
• Advanced English proficiency required.
• Must have unrestricted, permanent right to work in Mexico.
• Proficiency in industry-standard EDA tools like Cadence or Mentor Graphics.
• Experience in RTL-to-GDS implementation, static timing analysis, and power integrity.
• Knowledge of low-power design techniques and methodologies.

Culture & Benefits

• Hybrid work model allowing flexibility between on-site and off-site work.
• Opportunity to work at the forefront of semiconductor technology with industry experts.
• Collaborative environment focused on innovation and continuous improvement.
• Commitment to ethical hiring practices and RBA compliance.