System Performance Modeling Engineer/Architect (NPU)

TL;DR

System Performance Modeling Engineer/Architect (NPU): Building and maintaining full-chip performance models for NPU tile arrays and NoC to drive architecture decisions with an accent on cycle-approximate modeling and workload analysis. Focus on optimizing memory bandwidth, solving NoC contention, and correlating model predictions with RTL and silicon.

Location: Singapore

Company

hirify.global is a world-leading technology company specializing in Bitcoin mining solutions and AI cloud computing.

What you will do

• Build and maintain cycle-approximate and analytical models of the tile array, NoC, memory subsystem, and IO using C++, SystemC, and Python.
• Characterize LLM and CNN inference workloads to produce roofline and bottleneck analyses.
• Model NoC contention, memory bandwidth, and QoS under realistic traffic scenarios to parameterize architecture studies.
• Run architecture trade-off sweeps on tile count, memory size, and NoC topology to provide recommendations for architecture freeze.
• Partner with the AI compiler team on dataflow mapping, tiling, and scheduling to ensure models reflect achievable performance.
• Correlate model predictions against RTL, emulation, FPGA, and silicon to quantify and close the modeling-to-reality gap.

Requirements

• 5+ years of experience in performance modeling or architecture for SoCs, accelerators, GPUs, or CPUs.
• Strong proficiency in C++ and Python, with experience using SystemC or similar cycle-approximate modeling frameworks.
• Solid understanding of computer architecture fundamentals, including memory hierarchy, NoC behavior, and roofline reasoning.
• Demonstrated ability to translate modeling results into concrete architecture decisions.
• Ability to work effectively with incomplete specifications and collaborate across architecture, design, and software teams.

Nice to have

• Experience modeling AI/ML inference workloads (LLM, CNN, transformers) and analyzing quantization/precision effects.
• Familiarity with HBM, 3D-DRAM bandwidth analysis, or memory-controller behavior.
• Exposure to compiler and dataflow co-design for accelerators.
• Background with tile-based or dataflow architectures.

Culture & Benefits

• Inclusive environment with an open workspace and an exciting start-up spirit.
• Opportunity to collaborate with industrial pioneers in the digital asset and AI cloud industries.
• Culture of personal accountability, autonomy, and rapid professional growth.
• Attractive welfare benefits including training and mentoring opportunities.