Forward Error Correction Intern (FEC/DSP)

Location: Cordoba, Argentina

Company

hirify.global develops semiconductor solutions for enterprise, cloud, AI, and carrier data infrastructure.

What you will do

• Design and validate DSP and FEC algorithms for optical coherent transceivers.
• Design digital implementation architectures for hardware-based communication blocks.
• Develop software for communications-system simulation.
• Contribute to the reliability and validation of HDL-based ASIC blocks.
• Collaborate with engineers and scientists on advanced FEC/DSP schemes and optimization problems.

Requirements

• Currently pursuing an Engineering BS, MS, or PhD degree in Electronics, Computing, or Telecommunications.
• Knowledge of digital communication systems.
• Good system modeling skills.
• Programming skills in C, C++, Python, Verilog, and SystemVerilog.
• Good written and oral communication skills.

Culture & Benefits

• Part-time position within a collaborative, transparent, and inclusive environment.
• Competitive compensation and benefits.
• Access to tools and resources for professional growth and development.
• Applicants may be subject to U.S. export license review for access to export-controlled technology.

Hiring process

• Interviews evaluate individual experience, thought process, and communication skills in real time.
• AI tools, transcription apps, automated note-taking bots, and real-time answer generators are prohibited during interviews.