Staff Application Engineer

TL;DR

Staff Application Engineer (Mixed-signal/PHY SerDes): Support testing and system-level debugging, analyze bring-up and characterize silicon IPs (High-Speed SerDes, USB, PLL/DLL, ADC), and evaluate/debug new PHY features while developing driver firmware and collecting performance data. Focus on building and executing bench-level validation test plans with automated scripts, generating reports/application notes, and providing direct technical customer support to tune performance for system requirements.

Company

hirify.global provides semiconductor solutions for data infrastructure, including analog and mixed-signal technologies for communications and cloud markets.

What you will do

• Support internal teams with testing and system-level debugging.
• Analyze bring-up, debug, and characterize silicon-level internal IPs such as High-Speed SerDes, USB, PLL/DLL, and ADC.
• Evaluate and debug new PHY features, develop driver firmware, collect performance data, and resolve application/production issues (e.g., Ethernet and PCIe).
• Develop and execute bench-level validation test plans; automate testing with Python, VBA, and MATLAB scripts.
• Generate test reports and write application notes; provide technical support and collateral documentation for customers.
• Act as a primary technical interface with customers and qualify design activity at customer engineering level.

Requirements

• Bachelor’s degree in Computer Science, Electrical Engineering, or related field, plus 3–5 years of relevant experience (Master’s/PhD with 2–3 years experience may apply).
• Strong fundamentals in communication and transmission lines, EM, and microwave theories.
• Experience in integrated circuit characterization and creating/performing validation test cases with report generation.
• Hands-on debugging with lab equipment such as oscilloscope, power supplies, and multimeter.
• Fluent English (spoken and written).
• Location: onsite in Pavia, Italy, working from the office five days per week.

Nice to have

• Experience with TX/RX and PLL characterization of High-Speed SerDes ICs or RFICs.
• Experience using sampling scope, VNA, TDR, and BERT equipment.
• Experience testing IEEE/OIF Ethernet 802.3 standards or PCIe.
• Knowledge of high-speed SerDes PCB design and system application.

Culture & Benefits

• Full-time onsite role with an in-office work environment (5 days/week).
• Competitive base pay and benefits.
• Collaborative environment focused on transparency and inclusivity.
• Opportunities to grow and develop with the tools and resources needed to succeed.

Hiring process

• Interviews assess the appropriate level based on candidate experience; offers align with that level.
• Use of AI tools during interviews is not permitted and may lead to disqualification.

Salary: 40,500–54,000 EUR per annum

Location: Pavia, Italy (onsite, 5 days/week)