Associate Staff Design Verification Engineer (Embedded IoT)

TL;DR

Associate Staff Design Verification Engineer (SystemVerilog/UVM): Developing and executing verification plans for SoC/IP blocks and mixed-signal designs with an accent on SystemVerilog/UVM-based testbenches and functional coverage closure. Focus on debugging RTL and verification failures across simulation and emulation environments to ensure the reliability of Wireless MCU SoCs.

Location: Hybrid (Singapore)

Company

hirify.global is a leading innovator in low-power wireless connectivity, specializing in integrated SoCs for smart home, industrial IoT, and smart cities.

What you will do

• Develop and execute verification plans for SoC/IP blocks and mixed-signal designs.
• Build and maintain SystemVerilog/UVM-based testbenches.
• Drive functional coverage closure, assertions, and regression analysis.
• Debug RTL and verification failures across simulation and emulation environments.
• Collaborate with RTL designers, architecture teams, firmware/software, and validation engineers.
• Mentor junior engineers and contribute to the overall verification strategy.

Requirements

• BS/MS in Electrical or Computer Engineering.
• 5–10+ years of verification experience.
• Experience with Wireless SoCs, MCU subsystems, and embedded systems.
• Proficiency in AMBA/AXI/APB protocols.
• Strong knowledge of SystemVerilog, UVM/OVM, SVA, and low-power verification concepts.
• Ability to work with Python/Perl/TCL scripting.

Nice to have

• Experience with CDC/RDC and Mixed signal / AMS verification.
• Knowledge of CI flows and automation for verification methodologies.

Culture & Benefits

• Medical and dental insurance coverage including spouse and children.
• Bi-yearly health screenings and flu vaccinations.
• Convenient office location situated above Tai Seng MRT station.
• Highly skilled, tight-knit team environment with a focus on work-life balance.