Senior Mixed-Signal Behavioral Modeling Engineer (SoC)

TL;DR

Senior Mixed-Signal Behavioral Modeling Engineer (SoC): Developing high-level behavioral models for analog and mixed-signal IP with an accent on Verilog-AMS and SystemVerilog. Focus on building mixed-signal verification methodologies from scratch and integrating AMS models into UVM-based environments.

Location: Must be based in the United States (U.S. Person as defined by ITAR)

Salary: $160,000 – $230,000 + equity

Company

A Series C space startup mass-producing high-power satellite platforms for LEO to deep space missions.

What you will do

• Develop behavioral models for analog and mixed-signal IP (ADCs, DACs, PLLs, etc.) using Verilog, Verilog-AMS, or SystemVerilog.
• Create regression infrastructure and mixed-signal testbenches for co-simulation.
• Integrate AMS models into UVM-based digital verification environments.
• Define and build the mixed-signal verification methodology for top-level SoC and subsystem verification.
• Collaborate with analog/RF designers to capture real-world behaviors and map them to abstractions.
• Provide modeling and verification insights during architectural reviews and silicon bring-up.

Requirements

• M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or related field.
• 5+ years of experience in analog/mixed-signal modeling and/or AMS verification.
• Hands-on experience with SystemVerilog, Verilog-AMS, wreal/RNM, or equivalent.
• Strong understanding of PLLs, LDOs, ADC/DACs, RF/IF paths, and clocking.
• Must be a U.S. Person as defined by ITAR regulations.

Nice to have

• Experience with MATLAB/Simulink, Python, or SystemC AMS.
• Knowledge of signal processing theory or RF system modeling.
• Experience in cross-functional, geographically distributed teams.

Culture & Benefits

• Comprehensive benefits including medical, dental, and vision coverage.
• Paid time off and paid parental leave.
• Equity in the company.
• High-impact role in a fast-paced, groundbreaking space startup environment.