High Speed IO Validation Engineer (AI)

TL;DR

High Speed IO Validation Engineer (AI): Ensuring functional integrity and performance of high-speed interfaces for next-generation AI chips with an accent on SerDes PHYs, HBM, and PCIe. Focus on electrical characterization, link margin analysis, and cross-functional debugging of ultra-high bandwidth systems.

Location: Onsite in Seongnam, South Korea

Company

hirify.global is developing a next-generation AI Chip Ecosystem and data center solutions for AI accelerators.

What you will do

• Lead the bring-up, electrical characterization, and functional validation of high-speed interfaces including SerDes PHYs (PCIe, CXL, Ethernet) and HBM3E/DDR.
• Conduct thorough compliance and interoperability testing to ensure adherence to electrical specifications and protocol requirements.
• Perform detailed lab measurements using Oscilloscopes, BERTs, and VNAs for jitter, eye diagram, and link margin analysis.
• Collaborate with ASIC, SI, and Firmware teams to debug complex IO issues and identify root causes of performance degradation.
• Develop comprehensive test plans, validation reports, and technical documentation.

Requirements

• BS/MS in Electrical Engineering or equivalent practical experience.
• 5+ years of hands-on experience in high-speed IO validation and system debug for multi-Gbps speeds.
• Expertise in SerDes PHY performance validation, including TX equalization tuning and receiver adaptation.
• Proficiency in operating and automating high-speed test equipment (Oscilloscopes, VNA, TDR).
• Strong knowledge of physical layer architecture, equalization techniques (CTLE, DFE, FFE), and protocols (PCIe, CXL, Ethernet).
• Understanding of low-level firmware/driver architecture and its interaction with hardware systems.

Hiring process

• Document review followed by online and on-site interviews.
• Culture-fit interview and compensation negotiation.