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2 дня назад

Design Verification Engineer (ASIC)

Формат работы
hybrid
Тип работы
fulltime
Грейд
middle
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR

Design Verification Engineer (ASIC): Delivering high-quality mixed-signal IC solutions by performing end-to-end functional verification across block and chip-level designs with an accent on UVM-based testbench development and mixed-signal ASICs. Focus on implementing constrained-random test suites, driving coverage closure, and resolving complex timing-related issues in a technically rigorous environment.

Location: Hybrid; Must be based in Austin (TX), Chandler (AZ), or Greensboro (NC)

Company

A leader in mixed-signal processing providing innovative end-user solutions for the world's top consumer brands.

What you will do

  • Perform functional verification of custom mixed-signal ASICs at both block and chip levels.
  • Design and implement UVM-based testbenches, including infrastructure, scoreboards, checkers, and assertions.
  • Create directed and constrained-random test suites to ensure robust functional coverage and drive coverage closure.
  • Conduct failure analysis, regression triage, and debug of functional and timing-related issues.
  • Run and debug gate-level simulations, addressing timing violations and back-annotation issues.
  • Collaborate cross-functionally with analog/digital designers, firmware teams, and manufacturing test engineers.

Requirements

  • Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a related field.
  • Relevant experience: 2+ years for Bachelor's degree holders; 0+ years for Master's degree holders.
  • Strong proficiency with HDLs (Verilog/VHDL) and HVLs (SystemVerilog with UVM/OVM/AVM/Vera).
  • Hands-on experience with testbench architecture, stimulus generation, and coverage analysis.
  • Candidates must be able to access technical data without a requirement for an export license based on nationality.

Nice to have

  • Experience verifying mixed-signal ASICs in complex SoC environments.
  • Knowledge of signal processing concepts relevant to mixed-signal designs.
  • Experience with SystemVerilog Assertions (SVA).
  • Exposure to formal verification, hardware emulation, or software-driven verification.

Culture & Benefits

  • Award-winning culture built on inclusion, fairness, and meaningful community engagement.
  • Collaborative and technically rigorous work environment.
  • Focus on delivering enjoyable employee experiences and career growth.

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