System Software Engineer - Scalable Solution

TL;DR

System Software Engineer - Scalable Solution (NPU/HPC): Designing and implementing key components of a communication software stack including collective communication library and driver specifically engineered for NPU and related communication topologies with an accent on technical design, API definition, and performance optimization. Focus on analyzing performance bottlenecks, collaborating with hardware and software teams, and influencing future NPU and interconnect topology.

Location: Onsite at R-TOWER 3F ~ 8F, Jeongja-il-ro 156beon-gil, Bundang-gu, Seongnam-si, Gyeonggi-do, South Korea

Company

AI semiconductor company developing NPU hardware and high-performance software stacks.

What you will do

• Design and implement key components of communication software stack including collective communication library and driver for NPU topologies
• Contribute to technical design, API definition, and performance optimization across software and hardware layers
• Collaborate with hardware and software teams to analyze performance bottlenecks and influence NPU and interconnect topology

Requirements

• Minimum 5 years professional experience in systems software development or Ph.D. in HPC, Parallel Computing, Computer Architecture, Collective Communication, or equivalent
• Strong collaboration and problem-solving skills for complex technical issues
• Proficiency in low-level systems programming (C/C++) and understanding of OS internals and networking
• Proven experience developing and delivering complex, high-performance, reliable software in collaborative environment
• Understanding of hardware accelerators (GPUs, TPUs, NPUs) and their performance characteristics

Nice to have

• Solid understanding of collective communication algorithms (All-Reduce, All-Gather, Reduce-Scatter) and performance characteristics
• Prior experience with high-performance communication libraries (NCCL, MPI), parallel runtimes, high-performance networks (RDMA/RoCE, NVLink, CXL)
• Understanding of interconnect topologies and Network-on-Chip (NoC) architectures

Hiring process

• Document screening > Online interview (including coding test) > On-site interview (including assignment) > Compensation negotiation > Final offer
• Process may vary by role and schedule; results sent via email
• Early closure possible upon filling; false information leads to disqualification