Sr Staff Engineer, CPU System Microarchitect (AI)

TL;DR

Sr Staff Engineer, CPU System Microarchitect (AI): Designing and implementing CPU system RTL for high-performance RISC-V CPUs with an accent on core integration, fabrics, and subsystem components. Focus on optimizing power, performance, and area (PPA) through RTL experiments and microarchitecture definition.

Location: Hybrid; must be based in Austin, TX, Fort Collins, CO, or Santa Clara, CA

Salary: $100k - $500k

Company

hirify.global is leading the industry in cutting-edge AI technology, developing high-performance RISC-V CPUs and AI platforms.

What you will do

• Define and implement CPU system RTL, combining multiple cores, clusters, fabrics, and subsystem components.
• Collaborate with DV, PD, architecture, and performance teams to deliver functional, timing, and power-converged designs.
• Apply innovative techniques to optimize power, performance, and area (PPA).
• Partner with validation and test teams to ensure robust pre-silicon and post-silicon execution.
• Enhance the RTL design environment, tools, and methodologies to improve development efficiency.

Requirements

• 10+ years of industry experience with a strong background in CPU systems RTL and microarchitecture.
• Proficiency in RTL coding using Verilog or VHDL.
• Experience debugging RTL/logic across multiple design hierarchies in pre- and post-silicon environments.
• Expertise in microarchitecture definition, design specification, and performance-driven trade-off analysis.
• Must be eligible to access U.S. export-controlled technology (compliance with EAR).

Culture & Benefits

• Highly competitive compensation package.
• End-to-end exposure to CPU design from microarchitecture through timing and power convergence.
• Opportunity to design and optimize custom RISC-V CPU systems from first principles.
• Deeply technical and highly collaborative environment focused on solving cutting-edge hardware challenges.