Staff Digital Verification Engineer

TL;DR

Staff Digital Verification Engineer: Executing verification plans on digital IP blocks using simulation and formal verification techniques with an accent on UVM test benches. Focus on debugging IP and system-level issues, validating block power and performance requirements, and developing verification flows and methodologies.

Location: Austin, TX

Salary: $150,500 - $279,500 USD

Company

hirify.global is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives.

What you will do

• Create and execute test plans with emphasis on metrics-driven verification for block and IP verification.
• Develop constrained random tests, scoreboards, and coverage.
• Validate block power and performance requirements.
• Debug functional failures at subsystem and SoC levels.
• Architect and implement verification components using UVM-based methods.
• Develop verification flows and methodologies to enhance IP, SoC, and Formal Verification.

Requirements

• 10+ years of design experience.
• Bachelor's or Master's degree in Electrical/Computer Engineering.
• Strong knowledge of Verilog, SystemVerilog, UVM, and C/C++.
• Knowledge of digital design, ARM, or RISC-V architecture and bus protocols.
• Knowledge of scripting languages like Perl, Python, Tcl, and shell.
• Advanced verification skills in SVAs, constrained random stimulus, and coverage analysis.

Nice to have

• Mixed Signal verification with RNM and SPICE models.
• DSP, digital wireless, modulation schemes, FEC.
• Verification and debug of low-power design with UPF.
• Technical leadership and mentoring experience.

Culture & Benefits

• Great medical, dental, and vision plans.
• Highly competitive salary.
• 401k plan with match and Roth plan option.
• Flexible PTO schedule.
• Tuition reimbursement.
• Onsite gym and free snacks.