Design Verification Engineer Intern (Embedded)

TL;DR

Design Verification Engineer Intern (Embedded): Assisting in the development and verification of next-generation network switches with an accent on switch architecture, RTL verification, and methodology implementation. Focus on building complex object-oriented verification environments, debugging simulations, and ensuring tapeout quality for high-performance semiconductor infrastructure.

Location: Must be based in or able to work in Petah-Tikva, Israel

Company

A global leader in semiconductor solutions building essential infrastructure for data, cloud, and AI architectures.

What you will do

• Implement new features in design and verification flows.
• Develop complex object-oriented random verification environments using SystemVerilog and UVM.
• Write and execute verification test plans using random techniques and coverage analysis.
• Debug failures in simulation to identify root causes.
• Automate repetitive tasks and improve efficiency using scripting languages.
• Analyze and close code and functional coverage to meet high-performance targets.

Requirements

• Currently pursuing a BS/MS degree in CS/EE or related field.
• At least two years remaining until graduation.
• Strong understanding of object-oriented programming.
• Knowledge of digital logic design.
• Strong problem-solving and collaboration skills.
• Eligibility to access export-controlled information under U.S. law.

Culture & Benefits

• Work within a highly skilled development team focused on purposeful innovation.
• Environment fostering collaboration, transparency, and inclusivity.
• Hands-on learning with modern industry-standard tools and methodologies.
• Exposure to large-scale semiconductor development lifecycles.
• Professional growth opportunities in a global high-tech company.

Hiring process

• Evaluation of technical experience and problem-solving skills.
• Real-time interview process strictly prohibiting the use of AI tools or automated assistants.