Senior/Staff Physical Design Engineer (Embedded)

TL;DR

Senior/Staff Physical Design Engineer (Embedded): Leading the end-to-end design, implementation, and optimization of complex SoCs and IP blocks with an accent on physical design methodologies like synthesis, floorplanning, and timing closure. Focus on maximizing power, performance, and area metrics while driving EDA tool automation and ensuring successful tape-out readiness.

Location: Hybrid, Singapore (Tai Seng)

Company

hirify.global is a leading innovator in low-power wireless connectivity and embedded technology for smart home, industrial IoT, and smart city applications.

What you will do

• Execute full-cycle physical design from RTL handoff to GDSII.
• Define and implement strategies for floorplanning, clock-tree synthesis, placement, and routing.
• Optimize PPA metrics and manage complex design constraints.
• Collaborate with front-end, DFT, and packaging teams to ensure seamless system integration.
• Drive methodology enhancements and automate EDA tool flows for improved efficiency.
• Mentor junior engineers and support foundry-related tape-out processes.

Requirements

• 4+ years of experience in ASIC physical design.
• Bachelor’s or Master’s degree in Electrical Engineering, VLSI, or related field.
• Hands-on expertise with EDA tools such as Synopsys or Cadence.
• Strong background in timing analysis, low-power methodologies, and sign-off flows.
• Experience with chip-level integration and hierarchical design techniques.
• Ability to work in a hybrid environment based in Singapore.

Culture & Benefits

• Comprehensive medical and dental insurance coverage for employee and family.
• Employee Stock Purchase Program (ESPP).
• Bi-yearly health screenings and flu vaccinations.
• Hybrid work environment located near Tai Seng MRT station.
• Emphasis on work-life balance within a collaborative and impactful engineering team.