Senior Staff Design Verification Engineer (Embedded)

TL;DR

Senior Staff Design Verification Engineer (Embedded): Ensuring the correctness and functionality of complex Wireless MCU SoCs with an accent on analog and mixed-signal (AMS) cosimulation. Focus on building advanced verification environments using SystemVerilog and UVM to verify interactions between digital and analog blocks within highly integrated SoC designs.

Location: Singapore (Hybrid)

Company

hirify.global is a leading provider of silicon, software, and solutions for a smarter, more connected world, specializing in wireless connectivity and IoT technology.

What you will do

• Develop and maintain a robust cosimulation environment for digital RTL and analog/mixed-signal models.
• Create and implement SystemVerilog-based UVM testbenches for digital components.
• Define coverage plans and implement constrained-random sequences and agents.
• Analyze coverage metrics and address gaps in verification environments.
• Run regressions and file bug reports to ensure design quality.
• Collaborate with the IoT Digital team on complex Wireless MCU SoC verification.

Requirements

• 10-15 years of industry experience in design verification.
• Master’s or Bachelor’s Degree in Computer Science, Electrical Engineering, or related field.
• Proficiency in SystemVerilog, UVM, and Assertion-based Formal Verification.
• Familiarity with Verilog, Verilog A, C, and TCL.
• Experience with industry-standard interfaces and tools like Xcelium, Spectre, and Questasim.

Nice to have

• Scripting skills in Python or Perl.

Culture & Benefits

• Flexible work policy.
• Employee Stock Purchase Plan (ESPP).
• Comprehensive insurance plans with outpatient coverage.
• Opportunity to work in a global company focused on innovative IoT technology.