Sr. Staff Formal Verification Engineer

TL;DR

Sr. Staff Formal Verification Engineer: Developing and enhancing formal methodologies for audio and mixed-signal devices with an accent on formal and dynamic verification environments. Focus on mentoring engineers, supporting verification teams, and improving functional verification processes.

Location: Hybrid in Austin, Texas

Company

hirify.global is a company solving complex challenges with innovative end-user solutions for the world's top consumer brands.

What you will do

• Develop and enhance formal methodologies for design and verification teams.
• Mentor engineers in formal verification techniques and methodologies.
• Support the verification team in following and improving defined methodology practices.
• Develop test plans and verification methodologies to verify microarchitecture and design.
• Perform failure analysis and resolution, coverage analysis, and population.
• Implement and improve functional verification.

Requirements

• Master's degree in Electrical or Computer Engineering with 8+ years or PhD with 5+ years of formal verification experience.
• Expertise in designing and implementing formal verification environments for complex IP/module-level designs.
• Demonstrated ability to lead and drive the verification process from inception to completion.
• Excellent communication skills and a collaborative approach.
• Proficiency in System Verilog, UVM, or equivalent methodologies.
• Familiarity with scripting languages such as Python, Perl, TCL, Bash.
• Expertise in formal property languages, with SVA knowledge.
• Experience in property-based model-checking.
• Knowledgeable in Signal Processing, analog and digital design fundamentals.

Culture & Benefits

• Award-winning culture built on inclusion and fairness.
• Meaningful community engagement.
• Enjoyable employee experiences.