ASIC Design Verification Engineer

TL;DR

ASIC Design Verification Engineer: Verifying new designs for high-throughput Ethernet products using industry-proven constrained random methodologies with System Verilog and UVM, with an accent on coverage closure and understanding datapath flows. Focus on developing next-generation products that deliver unprecedented performance and power efficiency.

Location: Onsite at offices in USA (California) or Canada (Richmond).

Salary: $91,200 - $152,000 annually.

Company

hirify.global is a global technology leader designing, developing, and supplying semiconductor and infrastructure software solutions.

What you will do

• Verify new designs that can evolve rapidly in a dynamic market.
• Work on PCIe and other host interfaces using constrained random methodologies with System Verilog and UVM.
• Drive completion of verification via coverage closure.
• Contribute to developing next-generation high-throughput Ethernet products.
• Opportunity for technical leadership in all aspects of Design Verification.

Requirements

• Experience: BSEE + 8+ years or MSEE + 6+ years of related experience.
• Self-motivated with a strong sense of teamwork.
• Experience with constrained random verification methodologies.
• Proficiency in System Verilog (TB structures - Class, SVA, etc.) and UVM.
• Well-versed in Object-Oriented Programming (OOP).
• Good understanding of datapath flows.
• Familiarity with verification tools like VCS and Incisive.

Nice to have

• Experience with PCIe.
• Experience with using 3rd party BFM.
• Scripting skills (Python, Perl).

Culture & Benefits

• Competitive and comprehensive benefits package.
• Medical, dental, and vision plans.
• 401(K) participation including company matching.
• Employee Stock Purchase Program (ESPP).
• Company-paid holidays, paid sick leave, and vacation time.
• Opportunity to work on leading-edge technology.
• Be part of a successful product line in an extremely skilled and efficient group.