Staff IP Logic Design Engineer (Semiconductor)

TL;DR

Staff IP Logic Design Engineer (Semiconductor): Designing and developing RTL logic for industry-leading client chipsets with an accent on architecture and microarchitecture definition, and formal verifications. Focus on optimizing RTL for power, performance, area, and timing goals, ensuring high design integrity and seamless SoC integration.

Location: Fully home-based, must live and work from Singapore

Company

hirify.global is a leading technology corporation developing chipsets that power PCs used by millions worldwide.

What you will do

• Design and develop logic, write RTL, and run formal verifications for IPs.
• Contribute to architecture and microarchitecture definition for next-gen blocks.
• Optimize RTL and logic to meet power, performance, area, and timing goals.
• Review and strengthen verification plans, debug failing tests, and drive corrective actions.
• Support SoC customers for seamless IP integration and verification.
• Ensure high quality IP to SoC handoff through strong quality assurance practices.

Requirements

• Bachelor's degree in Electronics Engineering, Computer Engineering, Computer Science, or a closely related semiconductor field.
• Proven track record and demonstrated technical leadership in hardware development for semiconductor products.
• 12+ years of hands-on experience in pre-silicon verification or RTL logic design.
• Expertise with SystemVerilog, scripting languages (Python/Perl/Shell), power-aware simulation tools (VCS/Synopsys), RTL model builds, and DFT/DFV methodologies.
• Experience developing test plans, coverage strategies, and validation content aligned to high level silicon or IP architecture specifications.
• Familiarity with VLSI design flows, including structural and physical design processes, as well as SIP/HIP interoperability.
• Strong background in power-aware design and verification in modern low power semiconductor products.

Nice to have

• Experience with industry standard semiconductor bus and interface protocols such as AMBA, MIPI, USB, and PCIe.
• Solid understanding of chipset or CPU level power behavior, including power estimation and low power design techniques.
• In-depth expertise with PCI Express, including PCS, FEC, LTSSM, and high-speed data path microarchitecture.
• Deep knowledge of high-speed digital design, achieving timing closure at GHz frequencies using pipelining, retiming, and advanced microarchitectural techniques.
• Experience implementing low power optimization techniques such as clock gating, power gating, and power domain design.

Culture & Benefits

• Work in a collaborative and growth-driven environment.
• Opportunity to make real impact at a global scale.
• Be part of a high impact engineering team shaping the future of client chipsets.
• Fully home-based work model with occasional site visits based on business need.