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Principal DFT Engineer

Формат работы
hybrid
Тип работы
fulltime
Грейд
principal
Английский
b2
Страна
Canada
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR

Principal DFT Engineer (Semiconductor/Hardware): Architecting and implementing advanced Design for Test (DFT) and Design for Debug (DFD) methodologies and flows for integrated RTL-centric environments across IPs, ASICs, and SoC designs. Focus on automating DFT features, developing verification test benches, and ensuring robust timing checks.

Location: Toronto, Canada. The company offers a flexible work environment.

Company

hirify.global enables critical data communication, powering innovation in data centers, networking, AI, and autonomous vehicles.

What you will do

  • Act as a member of the central DFT methodology group, supporting flows across business units and projects.
  • Architect RTL-centric DFT/DFD methodologies and flows for IPs, ASICs, and SoC designs.
  • Automate RTL for advanced DFT/DFD features not supported by EDA vendors.
  • Develop automated verification test benches and sequences for DFT IP.
  • Build IP/block and SoC level scan insertion flows and scripting ATPG retargeting procedures.
  • Write static timing constraints, create waivers, and devise flows for bullet-proof timing checks.

Requirements

  • Bachelor's degree in Engineering Science, Electrical and Computer Engineering, or Computer Science.
  • 12+ years of experience in complex SoC designs in RTL, DFT, or FE capacity.
  • Vast experience with various DFT EDA tools from Siemens, SNPS, and Cadence.
  • Good knowledge and understanding of Verilog/VHDL and SystemVerilog.
  • Exposure to CAD and automation, including Perl, TCL, and Python.
  • Extensive experience with main DFT standards such as JTAG (1149.1/1149.6/1500), iJTAG (1687), and BIST techniques (memory BIST, logic BIST, interconnect BISTs).
  • Track record in integrating custom-made DFT logic for complex SoCs (System-On-Chip) and CoWoS (Chip-On-Wafer-On-Substrate) designs is highly desirable.
  • Experience in SoC and IP/Block level scan insertion and ATPG, simulation of zero delay and SDF annotated test sequences.

Culture & Benefits

  • Comprehensive health plans, Wellness Spending Account (WSA), and Employee Assistance Program (EAP).
  • Flexible time off options including paid vacation, paid holidays, and parental leave.
  • Additional compensation opportunities: Restricted Stock Units (RSUs), short-term incentive program, Retirement & Saving Programs, and Employee Stock Purchase Plan (ESPP).
  • Commitment to equal employment opportunity, diversity, and accommodation during the recruitment process.

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