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2 дня назад

Principal Engineer - Design For Test (DFT)

184 400 - 272 950$
Формат работы
onsite
Тип работы
fulltime
Грейд
principal
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR

Principal Engineer - Design For Test (DFT): Implementing and optimizing DFT/Test on complex IP and SOC designs with an accent on running Tessent tools, chiplet DFT solutions, and strong verification/debug skills. Focus on defining Design-for-Test architecture, enhancing methodologies, and leading a small team of DFT engineers.

Location: Onsite in Morrisville, NC, USA. Applicants must be eligible to access export-controlled information as defined under applicable U.S. export control laws and regulations, and may be subject to an export license review process prior to employment, except for U.S. citizens, lawful permanent residents, or protected individuals.

Salary: $184,400–$272,950 per annum

Company

hirify.global provides semiconductor solutions essential for the data infrastructure that connects our world, across enterprise, cloud, AI, and carrier architectures.

What you will do

  • Implement DFT/Test on complex IP and SOC for multiple custom/compute ASIC/SoC designs.
  • Run Tessent tools for insertion of DFT structures, including chiplet DFT solutions (Tessent SSN).
  • Collaborate with other leads to define Design-for-Test architecture and implement additional DFT/DFX features.
  • Be involved in STA constraint definition, pattern generation, and post-silicon bring-up and debug.
  • Mentor, guide, and drive a small team of DFT engineers.
  • Work with leads to enhance DFT methodologies and tools.

Requirements

  • Bachelor’s, Master’s degree or PhD in Computer Science, Electrical Engineering or related fields with a minimum of 10 years of work experience.
  • Direct DFT experience with at least 8 years in custom chip (ASIC) design.
  • Hands-on working experience in SCAN/MBIST/Validation/STA/IP-DFX/Post-Silicon Bring-up/Debug.
  • Thorough knowledge of various DFT/Test architecture solutions for 2.5D/3D IC design.
  • Understanding of DFT flows and methodologies and experience with Siemens/Synopsys Tool set (Tessent, Spyglass/Tmax, Genus, Modus, NCSim/DC).
  • Strong fundamentals in digital circuit design and logic design.
  • English: B2 required.
  • U.S. work authorization is required to access technology and/or software subject to U.S. export control laws and regulations.

Culture & Benefits

  • Exceptional, comprehensive benefits supporting financial well-being, family support, mental/physical health, and recognition.
  • Employee stock purchase plan with a 2-year look back.
  • Family support programs and robust mental health resources.
  • Recognition and service awards for contributions and milestones.
  • Commitment to fair hiring practices, prohibiting the use of AI tools during interviews.

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