Senior VLSI Process Design Engineer (VLSI)

TL;DR

Senior VLSI Process Design Engineer (VLSI): Optimizing hirify.global's process technology for power, performance, and area (PPA) in silicon designs, working at the intersection of process development and design implementation. Focus on identifying challenges and optimization opportunities, defining methodologies, and building tools for PPA optimization of hirify.global IPs.

Location: Hybrid in Israel, Haifa

Company

hirify.global is a product company dedicated to optimizing process technology to meet evolving design needs and deliver breakthrough silicon and platform solutions.

What you will do

• Conduct experiments to identify challenges and optimization opportunities in hirify.global's process technology.
• Drive continuous improvements in designs and methodologies across advanced technology nodes.
• Define methodologies and build tools to optimize Power, Performance, and Area (PPA) of hirify.global IPs.
• Analyze PPA results, derive insights, and communicate recommendations to stakeholders.
• Collaborate with Core and SoC design teams to optimize process requirements.
• Mentor and guide technical teams, fostering growth and best practices.

Requirements

• BSc or MSc in Electrical Engineering or Computer Engineering.
• 5+ years of hands-on experience in VLSI physical design with a proven track record of successful projects on advanced technology nodes.
• Basic scripting knowledge in Python and TCL.
• Good familiarity with physical design implementation flows and techniques, including floorplanning, placement, routing, and timing closure.
• Knowledge at the cell and transistor level.
• Deep understanding of the various factors impacting PPA trade-offs.

Nice to have

• Experience mentoring technical teams.

Culture & Benefits

• Hybrid work model allowing employees to split time between working on-site at an assigned hirify.global site and off-site.
• Team dedicated to optimizing hirify.global's process technology to meet evolving hirify.global designs needs.
• Drive continuous improvements in silicon designs and methodologies.
• Partner closely with Core and SoC design teams.
• Opportunity to contribute to strategic decision-making and product direction.
• Foster growth and best practices within technical teams.