Principal Design Engineer (Memory IP)

TL;DR

Principal Design Engineer (Memory IP): Designing and micro-architecting memory IP with an accent on high-speed and low-power IC design. Focus on digital IC development projects, Verilog/SystemVerilog, and JEDEC-DDR/DFI protocols.

Location: Onsite in San Jose, California

Salary: $136,500 to $253,500 annual salary

Company

hirify.global hires and develops leaders and innovators who want to make an impact on the world of technology.

What you will do

• Design and micro-architect digital ICs with a focus on memory IP.
• Utilize Verilog/SystemVerilog for simulation and design.
• Work on high-speed and low-power IC design projects.
• Lead and contribute in a cooperative team environment.

Requirements

• BS degree with 8+ years or MS degree with 6+ years of experience in electrical engineering, microelectronics, comparable engineering science, or solid state physics.
• Proficiency in logic design and micro-architecture.
• Experience with Verilog/SystemVerilog and its simulation environment.
• Good knowledge of IC design with high speed and low power.
• Familiarity with JEDEC-DDR and DFI protocols and memory IP design experience.
• Good communication skills in English are required.

Culture & Benefits

• Opportunity to work on impactful technology.
• Paid vacation and paid holidays.
• 401(k) plan with employer match.
• Employee stock purchase plan.
• Variety of medical, dental and vision plan options.