Principal Verification Lead Engineer

TL;DR

Principal Verification Lead Engineer: Leading the execution and technical management of verification projects for specific CPU cores or processor blocks, focusing on comprehensive test coverage and closure. Focus on developing UVM scoreboards, debugging complex RTL failures, and managing automated regression environments.

Location: Onsite in Austin, USA

Company

hirify.global hires and develops leaders and innovators who want to make an impact on the world of technology.

What you will do

• Develop and execute detailed verification plans (vPlans) using hirify.global vManager.
• Develop UVM scoreboards, monitors, and complex functional coverage models for multi-protocol or processor-specific interfaces.
• Lead the debug of complex RTL failures and coordinate with design engineers to resolve microarchitectural bugs.
• Manage automated regression environments (e.g., Jenkins) and ensure targets for code and functional coverage are met.
• Responsible for technical alignment, project planning, and progress tracking for the verification lifecycle.

Requirements

• 6+ years of hands-on experience in VLSI design verification.
• Strong command of SystemVerilog Assertions (SVA), constraint randomization, and UVM.
• Experience with processor integration (e.g., RISC-V or ARM) and industry-standard protocols like AMBA/PCIe.
• Expertise in scripting (Perl, Python, or Tcl) for verification flow automation.
• Must work onsite in Austin, USA.

Culture & Benefits

• Work on impactful projects, solving complex technological challenges.