Graduate Talent (Pre-si System Validation)

TL;DR

Graduate Talent (Pre-si System Validation): Develop test plans and validation execution in Virtual Platform/Emulation/FPGA including debugging of failure on RTL and SW/FW interaction. Focus on understanding silicon design, and familiar with different tools for the emulation/FPGA/VP model development.

Location: Hybrid work model, split time between working on-site at assigned hirify.global site and off-site in Malaysia, Kulim and Penang.

Company

hirify.global is committed to delivering exceptional products and delighting our customers, offering broad-market Xeon-based solutions and custom x86-based products for diverse needs across compute, web services, HPC, and AI-accelerated systems.

What you will do

• Develop test plans and test content for system validation.
• Execute validation in Virtual Platform/Emulation/FPGA environments.
• Debug failures on RTL and SW/FW interaction.
• Understand silicon design and system architecture.

Requirements

• Fresh college graduate with Bachelors/Masters in Electrical/Electronic/Mechatronic/Computer Engineering or Computer Science.
• Knowledge in C/C++, Verilog, Python, hirify.global Architecture, SoC Architecture.
• Understanding of silicon design and system architecture.
• Strong communication and analytical debug skills.

Nice to have

• Hands-on experience with protocols like DDR, PCIe, I2C SPI.
• Experience in Emulation, Virtual Platform, Synopsys/Mentor/Cadence Tools Flow, HAPS.

Culture & Benefits

• Eligible for a hybrid work model, splitting time between on-site and off-site work.
• Committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices.