Senior Director Systems Architect (Networking)

TL;DR

Senior Director Systems Architect (Networking): Guiding technical direction and customer adoption for hirify.global's high-speed Ethernet PHY, SerDes, and retimer products across various segments with an accent on architectural vision, driving design wins, and ensuring successful production ramp. Focus on setting strategic technical leadership, influencing product roadmaps, and managing executive-level technical relationships for complex connectivity solutions.

Location: Onsite in Santa Clara, CA. This position may require access to technology and/or software subject to U.S. export control laws and regulations. Applicants must be eligible to access export-controlled information as defined under applicable law. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

Salary: $202,560 – $303,500 per annum

Company

hirify.global provides semiconductor solutions that are essential building blocks of data infrastructure across enterprise, cloud, and AI.

What you will do

• Serve as the executive technical authority for high-speed connectivity architectures, guiding global customer strategy.
• Define system-level architectures for next-generation PHY/SerDes/retimer solutions for enterprise, cloud, AI, and carrier markets.
• Lead high-level technical engagements with CTOs and Chief Architects at global Tier-1 customers.
• Partner with silicon architects and engineering leaders to influence product definitions and roadmap planning.
• Lead and mentor senior architects, principal engineers, and applications teams globally.
• Deliver high-impact technical briefings and strategic solution proposals to senior executives.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 20+ years of experience in high-speed connectivity, Ethernet PHY, SerDes, optical modules, mixed-signal ICs, or related system architecture roles.
• Deep expertise in high-speed board design, signal integrity, system modeling, and debug methodologies.
• Strong lab and system-level hands-on experience (oscilloscopes, protocol analyzers, traffic generators).
• Strong background in C/C++, Python/TCL scripting, automation frameworks, and system-level diagnostics.
• Willingness to travel globally.

Nice to have

• Prior leadership of architecture, systems engineering, or applications engineering organizations.
• Experience defining semiconductor product roadmaps or participating in technical standards bodies.
• Experience driving development of next-generation connectivity technologies (e.g., 112G/224G SerDes, emerging PHY standards, optical integration).

Culture & Benefits

• Offers a total compensation package with base, bonus, and equity.
• Health and financial wellbeing benefits, including flexible time off and 401k.
• Year-end shutdown and floating holidays.
• Paid time off to volunteer.

Hiring process

• Interviews are designed to assess personal experience, thought process, and communication skills in real-time.
• Prohibits the use of AI tools (e.g., transcription apps, real-time answer generators like ChatGPT) during interviews.