Staff Engineer, Analog Layout

TL;DR

Staff Engineer, Analog Layout: Contributing to the development of High-Speed SerDes, Broadband Analog, and Computing/Storage-Memory Data-Transport products with an accent on functional blocks such as high-speed analog/digital, multi-GHz ADC/DAC, PLL/DLL serial and parallel I/O, and clock generation/distribution for custom ICs. Focus on running simulations and verifications using Cadence Virtuoso, collaborating with designers for iterative refinement, and ensuring designs meet specifications for state-of-the-art CMOS process technologies.

Location: Onsite in Singapore. This role involves collaborating with global teams across Argentina, Singapore, the U.S., and Europe.

Company

hirify.global provides essential semiconductor solutions that form the building blocks of global data infrastructure, enabling new possibilities across enterprise, cloud, AI, and carrier architectures.

What you will do

• Run simulations and verifications using Cadence Virtuoso, collaborating with designers for iterative refinement.
• Contribute to the development of High-Speed SerDes, Broadband Analog, and Computing/Storage-Memory Data-Transport products, including custom IC functional blocks.
• Participate as a key contributor in project lifecycles, attending routine technical meetings and mentoring.
• Provide progress updates and present solutions encountered during cutting-edge technology development.
• Engage in continuous learning and knowledge-sharing within the team.

Requirements

• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and at least 8+ years of professional experience or Master’s degree with 5+ years of experience.
• Deep understanding of layout methodology from initial chip planning to tape-out and parasitic optimizing.
• High-level proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc. reports.
• High-level proficiency/knowledge of Synopsys or CADENCE layout entry tools.
• Proven record of laying out high-performance analog circuits in state-of-the-art CMOS process technologies, performing top-level integrations, and placing products into volume production multiple times.
• Proficient in spoken and written English.
• Applicants may be subject to a U.S. export license review process prior to employment, except for U.S. citizens, lawful permanent residents, or protected individuals.

Nice to have

• Experience in advanced process technology and Fin-FET.
• Programming skills in Skill, Ample, or Perl.

Culture & Benefits

• Work in an environment of shared collaboration, transparency, and inclusivity.
• Receive competitive compensation and great benefits.
• Tools and resources provided to succeed, grow, and develop.
• Commitment to fair and authentic hiring practices, with a request not to use AI tools during interviews.