Digital Verification Engineer

TL;DR

Digital Verification Engineer (IC): Verifying the digital functions of mixed-signal products, implementing scalable testbenches and developing behavioral models. Focus on achieving coverage goals and contributing to digital verification methodology improvements.

Location: Based in Manila office

Company

hirify.global develops mixed-signal products.

What you will do

• Contribute to the digital verification plan based on system-level specification.
• Implement a suitable digital verification environment using industry standard methodologies (e.g. UVM).
• Create behavioral models of non-digital functions to enable system simulation and verification.
• Create test cases and sequences to cover all items in the verification plan and meet coverage requirements.
• Maintain a regression environment for automatically verifying digital/system functions.
• Generate design documentation and participate in design reviews.

Requirements

• MSc/MEng or PhD in Electronics Engineering or related subject.
• Minimum 3 years experience in digital IC verification using industry standard verification methods.
• Good knowledge and understanding of best-practice digital verification methods (e.g. UVM, SVA, coverage, etc.).
• Conversant with the SystemVerilog standard.
• Familiar with writing digital verification plans based on system-level specification documents.
• Proven experience implementing a full digital verification environment for a mixed-signal IC.

Nice to have

• Experience using additional digital verification methods (formal, linting, etc.).
• Experience with scripting languages such as TCL/Python.
• Experience producing accurate and complete documentation.