Senior Rtl Design Engineer (Semiconductor)

TL;DR

Senior Rtl Design Engineer (Semiconductor): Leading functional specification development and microarchitecture design for advanced digital systems and SoCs with an accent on RTL debugging, lint and CDC checks, and collaboration across teams. Focus on designing high-performance blocks, synthesis optimization, and power efficiency techniques.

Location: Remote with offices in Lviv, Odesa, Rivne, Kyiv, Ukraine

Company

hirify.global Engineering is a global leader in engineering services, providing R&D and digital technology solutions across industries including autonomous cars and robotics.

What you will do

• Lead functional specification development for advanced digital systems
• Design and implement microarchitecture for high-performance blocks
• Perform RTL debugging and ensure design correctness
• Run and analyze lint and CDC checks
• Collaborate with verification, physical design, and architecture teams
• Contribute to front-end synthesis and optimization (bonus)

Requirements

• 7+ years of hands-on experience in digital design
• Strong knowledge of Verilog and/or VHDL
• Familiarity with SystemVerilog and synthesis tools like Cadence Genus or Synopsys Design Compiler
• Bachelor's degree in EE, ECE, CE, CS or related field; MS or PhD highly desired
• Excellent communication and collaboration skills
• Location: Must be able to work remotely or from offices in Ukraine (Lviv, Odesa, Rivne, Kyiv)

Nice to have

• Experience with SoC-level integration and design
• Power optimization techniques for energy-efficient designs

Culture & Benefits

• Health insurance from day one regardless of probation
• Christmas holidays from December 25 to 31
• Support for veterans and psychological rehabilitation initiatives
• Flexible work environment and competitive compensation
• Opportunities for technical leadership and career growth