Design Verification Intern (Semiconductor)

Location: Petah-Tikva, Israel. The role may be hybrid, remote, or in-office.

Company

hirify.global develops semiconductor solutions that form essential building blocks for enterprise, cloud, AI, carrier, telecom, and automotive data infrastructure.

What you will do

• Verify circuitry inside multi-core CPU processors and Radio Access SoCs against customer specifications.
• Work with RTL engineers to verify Verilog designs using SystemVerilog for debugging.
• Run simulations with Synopsys VCS or a similar tool and debug issues until specifications are met.
• Collaborate with DFT engineers working on parallel blocks and communicate progress, issues, and schedule deviations.
• Present test plans and schedules to review committees for larger blocks.

Requirements

• Bachelor’s degree in Electrical Engineering or Computer Engineering plus 2–3 years of related professional experience, or a Master’s degree and/or PhD in these fields.
• Coursework in analog classes, Verilog or VHDL, basic circuits, and computer architecture.
• Focus in VLSI or course projects directly related to chip design.
• Experience with Synopsys, Cadence, Mentor, or a similar simulation tool, including writing and debugging a testbench.
• Comfort working in a Linux environment and scripting with Python.
• Strong attention to detail and willingness to iterate designs until fully refined.
• Ability to work and communicate effectively with the team and provide regular progress updates.
• Applicants must be eligible to access export-controlled technology and software under applicable U.S. export control laws; some applicants may require export license review before employment.

Culture & Benefits

• Full-time employment with competitive compensation and benefits.
• Collaborative, transparent, and inclusive work environment.
• Resources and development opportunities to support meaningful technical work.
• AI tools are not permitted during interviews unless specifically authorized by the interviewer; unauthorized use results in disqualification.