ASIC Project Engineer (Quantum Computing)

Location: Broomfield, Colorado, United States; hybrid, with employees expected to work at the assigned location and remote work permitted up to 2 days per week with approval.

Salary: USD 137,000–184,000 per year.

Company

Quantum computing company developing a full-stack platform for real-world applications across pharmaceuticals, materials science, financial services, government, industrial sectors, and research institutions.

What you will do

• Lead ASIC development programs supporting the Apollo and Lumos quantum-computing roadmaps.
• Coordinate ASIC design, fabrication, packaging, qualification, testing, and system integration with foundries, test providers, and external technology partners.
• Manage schedules, milestones, deliverables, critical paths, budgets, risks, acceptance criteria, and Statements of Work.
• Coordinate engineering, procurement, finance, legal, quality, program-management, design, architecture, packaging, and test activities.
• Facilitate technical and program reviews and prepare executive-level status reports, metrics, and communications.
• Help mature enabling technologies including advanced packaging, cryogenic electronics, ion-trap integration, and next-generation semiconductor processes.

Requirements

• Bachelor’s degree minimum; relevant fields include engineering, physics, business, supply chain, program management, or a related technical discipline.
• At least 2 years of experience managing complex technical programs involving external suppliers or development partners.
• Must be a U.S. Person: U.S. citizen, permanent resident or green card holder, or worker granted asylum or refugee status.
• Experience establishing strategic supplier relationships and tracking supplier execution, schedule deviations, risks, and corrective actions through closure.
• Direct experience with semiconductor foundries, OSATs, ASIC development partners, tape-outs, wafer fabrication, packaging, or qualification.
• Familiarity with PDKs, process nodes, mask sets, wafer lots, yield analysis, reliability testing, and semiconductor test flows.
• Experience with advanced packaging such as bump bonding, wafer-level packaging, interposers, TSVs, hybrid bonding, or 2.5D/3D integration.
• Ability to translate technical objectives into clear supplier requirements, deliverables, and program plans, while coordinating contractual, legal, intellectual-property, procurement, and commercial matters.
• Ability to work independently in a rapidly evolving R&D environment and quickly understand emerging semiconductor and quantum-computing technologies.
• Must have work authorization that does not now or in the future require U.S. employment-visa sponsorship.

Nice to have

• Experience supporting advanced R&D programs involving quantum-computing hardware, ion traps, cryogenic electronics, MEMS, photonics, or related technologies.
• Willingness and ability to learn technical goals involving foundry products, ASICs, advanced packaging, cryogenic electronics, and ion-trap technologies.

Culture & Benefits

• Fast-paced, multifunctional, R&D-focused environment valuing initiative, organization, technical curiosity, and close collaboration.
• Flexible work arrangements supporting work-life balance, subject to the role’s assigned-location and hybrid requirements.
• Employer-subsidized medical, dental, and vision insurance.
• 401(k) retirement savings plan with company match, student loan repayment benefit, equity opportunities, paid time off, sick leave, 12 paid holidays, and paid parental leave.
• Pre-employment drug testing is required for safety-sensitive positions.