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5 дней назад

Software Development Engineer (FPGA)

Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
Malaysia
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Software Development Engineer (FPGA) (DSP/RTL): Designing and developing FPGA foundation IP, programmable DSP slices, and IP Catalog tooling with an accent on RTL implementation, DSP algorithms, and functional validation. Focus on building multipliers, accumulators, filters, and arithmetic units, analyzing timing performance, and integrating DSP IP into simulation and synthesis flows.

Location: Penang, Malaysia. The role requires satisfactory proof of the right to work in Malaysia.

Company

hirify.global develops low-power programmable logic solutions, FPGA, CPLD, and programmable power management devices.

What you will do

  • Design and implement DSP-centric foundation IP blocks, including multipliers, accumulators, FIR/IIR filter primitives, and arithmetic units for FPGA integration.
  • Develop RTL in VHDL, Verilog, and SystemVerilog for DSP hard macros and programmable DSP slices.
  • Perform functional simulation and timing analysis to validate correctness and performance.
  • Collaborate with software and tools teams to model DSP IP in simulation libraries and synthesis flows.
  • Support FPGA software release activities, including requirements analysis, feature scoping, development, testing, validation, and maintenance of existing tools.
  • Improve test coverage and product quality for FPGA software tools.

Requirements

  • Bachelor’s or Master’s degree in Electronics/Electrical Engineering, Computer Engineering, or a related discipline.
  • 6 or more years of experience in IP design or ASIC/FPGA engineering.
  • Strong proficiency in RTL design using Verilog, VHDL, or SystemVerilog.
  • Working experience with DSP theory and algorithms, including filtering, FFT, fixed-point arithmetic, and sample-rate conversion.
  • Successful background and reference checks are required.

Nice to have

  • Experience with functional verification methodologies, including SystemVerilog Assertions and formal verification.
  • Familiarity with synthesis and static timing analysis tools such as Synopsys Design Compiler, PrimeTime, Radiant, Quartus, or equivalent.
  • Working knowledge of FPGA architectures and programmable DSP slice design.

Culture & Benefits

  • Full-time position within an international engineering and manufacturing organization.
  • Work in a fast-paced, results-oriented, team-first environment focused on R&D, product innovation, and customer service.
  • Comprehensive compensation and benefits programs are provided.
  • Diversity of individuals, ideas, perspectives, insights, and values is supported.

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