TD Memory Quality and Reliability PhD Intern (Semiconductors)

Location: Hybrid work model with on-site work at an assigned hirify.global site; primary location in Folsom, California, with additional locations in Santa Clara, California, and Hillsboro, Oregon, United States

Annual salary range: $120,898–$120,902 USD

Company

hirify.global develops semiconductor technologies and advanced process nodes, supporting memory technology certification and foundry technology readiness.

What you will do

• Analyze silicon characterization data from SRAM, Register File, and Fuse memory test structures to identify trends, variability, and risks.
• Support memory characterization across voltage, temperature, and process conditions.
• Perform data analysis, visualization, and reporting using Python, JMP, or similar tools.
• Develop statistical models for Vmin/Vmax prediction and technology readiness assessments.
• Support Silicon-to-Simulation correlation studies, certification reviews, and risk assessment activities.
• Collaborate with Design, Device Engineering, Process Integration, Product Development Engineering, and Yield Engineering teams; present findings and recommendations.

Requirements

• Currently pursuing a Ph.D. in Electrical Engineering or a related field.
• Basic knowledge of semiconductor devices, microelectronics, or integrated circuit design.
• Programming or scripting experience using Python or similar languages.
• Experience analyzing technical, scientific, or research data through academic projects, research activities, or previous internships.
• Cumulative GPA of 3.0 or higher required.

Nice to have

• Coursework, research, or experience in SRAM or memory technologies, semiconductor device physics, VLSI design, statistics, machine learning, data science, or semiconductor process technology.
• Experience with Python, Pandas, NumPy, JMP or other statistical analysis tools, data visualization, statistical modeling, large-scale data analysis, or predictive modeling.
• Experience in memory architectures, silicon characterization, reliability assessment, or semiconductor test methodologies.

Culture & Benefits

• Full-time student internship on Shift 1 in the United States.
• Hybrid work model allowing time to be split between on-site work at the assigned hirify.global site and off-site work.
• Compensation package includes competitive pay, stock bonuses, health benefits, retirement benefits, and vacation.
• Work includes collaboration with cross-functional semiconductor engineering teams and exposure to technology qualification and certification workflows.