Chief Memory Chip Design Engineer & Architect (Memory)

Location: San Jose Great Oaks Headquarters, San Jose, California, United States

Salary: $242,900–$323,800 per year

Company

hirify.global builds storage systems and infrastructure for AI-driven data centers, cloud platforms, and enterprise environments, combining engineering expertise with global-scale manufacturing.

What you will do

• Own end-to-end product architecture from concept through silicon qualification and serve as the final technical authority across design, process, and product engineering.
• Define memory subsystem architecture covering arrays, periphery, I/O, redundancy, test, and reliability, and translate product requirements into design specifications.
• Drive floorplanning and physical architecture, including array efficiency, periphery partitioning, power delivery, and die-level signal integrity.
• Own the multi-generation roadmap for node migration, density scaling, and performance scaling.
• Arbitrate trade-offs across process integration, circuits, DFT, packaging, and controller/firmware interfaces.
• Own design methodology and EDA/CAD strategy, mentor senior and principal engineers, and represent architecture to executives, customers, foundry partners, and standards bodies.

Requirements

• MS or PhD in electrical engineering, computer engineering, or a related field.
• 15+ years of memory or mixed-signal IC development experience, including 5+ years as an architect or chief engineer.
• Ownership of at least two memory products from architecture through production silicon.
• Deep advanced CMOS FinFET expertise covering layout, variability, reliability, and design for manufacturability.
• Broad memory architecture experience across DRAM, NAND/NOR, SRAM, and emerging non-volatile memory, with deep expertise in one area.
• Experience with modern Cadence and Synopsys custom and digital flows through full-chip sign-off.
• Experience owning EDA/CAD strategy and leading multi-site programs through influence.

Nice to have

• Embedded memory IP integration into SoCs and memory-controller co-design.
• Foundry engagement on PDKs, test chips, and design-technology co-optimization.
• Emerging non-volatile memory architecture experience, along with JEDEC involvement, patents, or publications.

Culture & Benefits

• Full-time exempt employment at the San Jose Great Oaks headquarters.
• Benefits include paid vacation and sick leave, medical, dental, and vision insurance, life and disability insurance, flexible spending and health savings accounts, and an employee assistance program.
• Additional benefits may include tuition reimbursement, transit support, employee stock purchase opportunities, and the WD Savings 401(k) Plan.
• Eligible employees may be considered for short-term incentives, long-term incentives, restricted stock units, or cash equivalents under applicable plans.
• hirify.global provides equal employment opportunities and an inclusive workplace, with accommodation support available during the application process.

Hiring process

• The anticipated application deadline is January 9, 2027, although the posting may close earlier if the role is filled.
• Applicants requiring an accommodation should contact the provided accommodations email with the requested accommodation, job title, and requisition number.